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Dr. Basant K Mohanty » SUIIT Index

Dr. Basant K Mohanty

Director Sambalpur University Institute of Information Technology
Website: Google Scholar
Photo of Dr. Basant K Mohanty

Biographical Info

Ph.D. (VLSI for Signal Processing), 2000, Berhampur University, Berhampur, Odisha

 

Post-doctoral Research:

SCE, Nanyang Technological University, Singapore, 2014-2015

Qatar University, Doha, Qatar, 2012-2013.

 

Area of Specialization

  • VLSI for Digital Signal Processing

 

Teaching Experience (29 years)

S.N Designation Organization/Institution Date of joining Date of leaving Duration (Years)
1 Professor& Associate Dean MPSTME, Shirpur campus,  SVKM’s NMIMS 02.07.2018 25.08.2021 3
2 Professor Jaypee University of Engineering and Technology, Guna, M.P 01.08.2007 30.06.2018 11
3 Asso. Professor Jaypee University of Engineering and Technology, Guna, M.P 01.07.2005 31.07.2007 2
4 Asst. Professor Jaypee University of Engineering and Technology 21.8.2003 30.06.2005 2
5 Asst. Professor Mody Institute of Technology and Science, Sikar, Rajasthan 28.7.2002 16.08.2003 1
6 Lecturer Birla Institute of Technology and Science, Pilani, Rajasthan 04.09.2001 21.7.2002 ~1
7 Jr. Lecturer SKCG College, (Autonomous, Govt. of Odisha), Paralakhemundi, Odisha 10.10.1992 31.08.2001 9

 

Administrative Experience

S.N Designation Organization/Institution Date of joining Date of leaving Duration (Years)
1 Director Sambalpur University Institute of Information Technology 28.08.21 continuing
2 Associate Dean & HoD, Electronics and Tele-communication Engineering, Mechatronics Engineering MPSTME, Shirpur campus,  SVKM’s NMIMS 02.07.2018 25.08.2021 03
3 HoD, Electronics and Communication Engineering, Jaypee University of Engineering and Technology, Guna, M.P 23.4.2014 24.04.2017 03
4 HoD, Electronics and Communication Engineering, Jaypee University of Engineering and Technology, Guna, M.P 21.08.2003 31.07.2007 04

 

 

Awards & Achievements:

  • 2018 Sydney R. Parker Best Paper Award, Circuits Systems and Signal Processing
  • 2018 M.N.S. Swamy Best Paper Award, Circuits Systems and Signal Processing,
  • Research Fellowship, Nanyang Technological University, Singapore
  • Research Fellowship from Qatar University, Qatar.
  • Received Rashtriya Gaurav Award, (2012) conferred by India International Friendship Society, New Delhi.

 

Research Grant:

Received INR 24.57 Lakhs from Science and Engineering Research Board (SERB), Department of Science and Technology (DST)

 

PhD Thesis Supervised:

S.N Name of scholar Title of Thesis Year of Award of degree Co-guide (If any)
1 AnuragMahajan Memory-efficient concurrent VLSI architecture for two-dimensional discrete wavelet transform May, 2014 Nil
2 Sujit Ku Patel High-performance VLSI Architecture for  FIR  Adaptive Filter August 2016 Nil
3 Subodh Ku Singhal Scalable Architecture for  VLSI  implementation of DSP Algorithms July 2017 Nil
4 VikasTiwari* Efficient VLSI Architecture for DWT and DWPT based on data-path study Dec.2017 Nil
5 AbhishekChoubey+ Parallel VLSI Architecture for lifting 2-D DWT using radix-8 Booth multiplier Dec. 2017 Nil
6 Rehan Ahmed Classification and prediction of stages of kidney health using ultrasound images ongoing Nil
7 Sachin Sonawane An artificial intelligent grain quality evaluation system for Indian Grading standards ongoing Nil

*received  young scientists award for his research work during 2012-2013.

+received Sydeny Parker and M.N.S.Swamy Best paper award, 2018.

 

 

Professional Membership:

  • Senior Member, IEEE
  • Life Member, IETE

 

 

 

Publications:

 

Refereed Journals   (SCI and SCOPUS Indexed)

 

 

S.N Paper details IF
1 S. Sonawane and B. K. Mohanty, An Improved Image Processing Scheme for Automatic Detection of Harvested Soybean Seeds, Journal of Food Measurement and Characterization, Springer, SCI (Accepted) 2.74
2 R. Ahmed and B. K. Mohanty, Chronic kidney disease stage identification using texture analysis of ultrasound images, Biomedical Signal Processing and Control, ELSEVIER, Vol. 69, August 2021, 102695, SCI 3.88
3 B. K. Mohanty, Parallel VLSI Architecture for Approximate Computation of Discrete Hadamard Transform, IEEE Transactions on Circuits and Systems for Video Technology, ISSN: 10518215, Vol.30, No.12, pp.4944-4953, Dec 2020, SCI 4.13
4 B. K. Mohanty and P.K.Meher, “An efficient parallel DA-based fixed-width design for approximate inner-product computation”, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Regular Papers, Vol.28, No.5, pp.1221-1229, May 2020, SCI 2.03
5 A. Choubey, and B. K. Mohanty, “Best paper award for 2018”, Circuits, Systems, and Signal Processing, Springer, ISSN- 0278081X, Vol.39, No.1, Jan. 2020, https://doi.org/10.1007/s00034-019-01336-2
6 S. K. Singhal, B. K.Mohanty, S. Patel, G. Saxena, “Efficient Diminished-1 Modulo (2n +1) Adder using Parallel Prefix Adder, Journal of Circuits, Systems, and Computers. Vol.29, No.12 (2020),2050186, DOI:10.1142/S0218126620501868, SCI 1.363
7 B. K. Mohanty and P.K.Meher, “Area-Delay-Energy Efficient VLSI Architecture for Scalable In-place Computation of FFT on Real Data”, IEEE Transaction on Circuits and Systems-I, Regular Papers, ISSN- 15498328, Vol.66, No.3, pp.1042-1050, Mar. 2019. SCI 3.318
8 B.K.Mohanty, “An efficient fixed-width adder-tree design using approximate computation”, IEEE Transaction on Circuits and Systems-II, Express Briefs, ISSN: 15497747, Vol.66, No.2, pp.192-196, Feb. 2019, SCI 2.83
9 A. Choubey, and B. K. Mohanty, “Novel Data Access Scheme and Efficient Parallel Architecture for Multilevel 2-D DWT,” Circuits, Systems, and Signal Processing, Springer, ISSN- 0278081X, DOI: 10.1007/s00034-018-0775-y, Vol. 37, No.10, pp.4482-4503, Oct. 2018, SCI (Received Best Paper Award: 2018 Sydney Parker Award, 2018 M.N.S. Swamy Best Paper Award among all paper published in 2017 and 2018) 1.68
10 Vasundara, B. K. Mohanty, G. Panda and N. B. Puhan, “Hardware design for VLSI implementation of acoustic feedback canceller in hearing aids”, Circuit, Systems and Signal Processing, Regular Papers. ISSN- 0278081X, DOI: 10.1007/s00034-017-0619-1, Vol. 37, pp.1383-1406, Mar 2018, SCI 1.68
11 A. Choubey and B. K. Mohanty, “A Block Based Area- Delay Efficient Architecture for Multi-level Lifting 2-D DWT,” International Journal of Computer Applications”, ISSN: 0975 – 8887, Vol. 169, No.4, July 2017
12 B. K. Mohanty and Abhisek Choubey, “Efficient design for Radix-8 Booth Multiplier and its application inlifting 2-D DWT”, Circuit, Systems and Signal Processing, Regular Papers. ISSN- 0278081X, Vol.36, No.3, pp-1129-1149, Mar, 2017, SCI 1.68
13 B. K. Mohanty, G. Singh, and G. Panda, “Hardware design for VLSI implementation of FxLMS and FsLMS based active noise controllers”, Circuits Systems and Signal Processing, Regular Papers, ISSN- 0278081X, Vol.36, No.2, pp. 447-473, Feb. 2017, SCI 1.68
14 V. Tiwari and B. K. Mohanty, Area-delay efficient flipping 2-D DWT structure using PEB Booth multiplier” International Journal of Computer Application, ISSN: 0975 – 8887, vol.146, no.13, pp. 36-38, July 2016. ISSN: 0975 – 8887,
15 B. K. Mohanty, P.K.Meher and S. K. Patel, “LUT optimization for distributed arithmetic based block least mean square adaptive filter”, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Regular Papers, , ISSN-10638210, Vol.24, No.5, pp.1926-1935, May 2016, SCI 1.68
16 B. K. Mohanty, P.K.Meher, S.K.Singhal, and M.N.S.Swamy, “A High-Performance VLSI Architecture for Reconfigurable FIR using Distributed Arithmetic”, Integration, the VLSI journal, Elsevier, ISSN- 01679260, Vol.54, pp. 37-46, June 2016, SCI 1.214
17 S.K.Singhal and B. K. Mohanty“Efficient parallel architecture for fixed-coefficient and variable-coefficient FIR filters using distributed arithmetic”, Journal of Circuits, Systems, and Computers (JCSC), ISSN-02181266, Vol. 25, No. 7, pp. 1650073-1-1650073-19, March 2016, SCI 1.32
18 B. K. Mohanty and P.K.Meher, “A high-performance FIR filter architecture for fixed and reconfigurable applications”, IEEE Transaction on Very Large Scale Integration (VLSI) Systems. ISSN-10638210, Vol. 24, No.2, pp. 444-452, Feb. 2016, SCI 2.03
19 B. K. Mohanty and S.K.Singhal, “Area-delay and energy-efficient architecture for VLSI implementation of SDR channnelizer”, Circuit, Systems and Signal Processing, Vol. 35, No. 88, pp. 2958-2971, October, 2016, SCI 1.68
20 P.K.Meher, B. K. Mohanty, S. Patel, S.Ganguly and T. Srikanthan, “Efficient VLSI architecture for decimation-in-time fast Fourier transform of real-valued data”, IEEE Transaction on Circuits and Systems-I, Regular Papers, ISSN- 15498328, vol.62, no.12, pp.2836-2845, Dec.2015. SCI 3.318
21 B.K.Mohantyand S. K. Patel, “Efficient very large scale integration architecture for variable length block least mean square adaptive filter”, IET Signal Processing,. DOI:10.1049/iet-spr.2014.0424, ISSN 17519683, Vol.9, No.8, pp.605-610, October 2015, Citation index/Citation per doc: 1.523, SNIP: 1.000, SJR: 0.458, Impact Factor: 1.298, H- Index: 28, Google Citation: 2; SCI 1.692
22 H.Rabah, A. Amira, B. K. Mohanty, S. Maadeed, and P. K.Meher, “FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, ISSN-10638210, Vol. 62, No.1, pp. 2209-2220, Oct. 2015, SCI 2.03
23 B. K. Mohanty, “Novel block formulation and area-delay-efficient reconfigurable interpolation FIR filter architecture for multi-standard SDR applications”, IEEE Transaction on Circuits and Systems-1, Regular Papers. ISSN- 15498328, Vol. 62, No.1, pp.283-291, Jan. 2015. SCI 3.318
24 B.K.MohantyandVikasTiwari, “Modified probabilistic estimation bias formulation for hardware efficient fixed-width Booth multiplier”, Circuit, Systems and Signal Processing, Springer, Vol.33, No.12, 3981-3994, Dec., 2014, SCI. 1.68
25 B. K. Mohanty and S. K. Patel, “Area-delay-power efficient carry select adder”, IEEE Transaction on Circuits and Systems-II, Express Brief, ISSN: 15497747, Vol.61, No.6, pp.418-422, Jun. 2014, SCI 2.82
26 B. K. Mohanty and P.K.Meher, “Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation”, IET Image Processing, ISSN: 17519659, Vol.8, No.6, pp. 345-353, June 2014, SCI 1.995
27 P.K. Meher, S.Y. Park, B. K. Mohanty, L.K. Seong and Y. C. Hao, “Efficient integer DCT architecture forHEVC”, IEEE Transaction on Circuits and Systems for Video Technology, ISSN: 10518215, Vol.24, No.1,pp.168-178, Jan. 2014, SCI 4.13
28 B. K. Mohanty, P.K. Meher, S.A. Madeed, and A. Amira, “Memory footprint reduction for power-efficient realization of 2-D finite impulse response filters”, IEEE Transaction on Circuits and Systems-I, Regular Papers, ISSN: 15498328, Vol.61, No.1, pp.120-133, Jan. 2014, SCI 3.318
29 B. K. Mohanty and AnuragMahajan, “Scheduling Scheme and parallel architecture for computation of multilevel lifting 2-D DWT without using frame-buffer”, IET, Circuit, Device and Systems, ISSN:1751858X, Vol.7, No.6, pp.319-325, Nov. 2013, SCI 1.292
30 B. K. Mohanty and Anurag Mahajan, “Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT”, ASP Journal of Low-power Electronics, Vol.9, No.1, pp.1-8, April 2013, ISSN:15461998, SNIP: 0.388, SJR: 0.21, Impact Factor: 0.62, SCOPUS 0.62
31 B. K. Mohanty and P.K. Meher, Memory-efficient high-speed convolution-based generic structure for multilevel 2-D DWT”, IEEE Transaction on Circuit and System for Video Technology, Vol.23, No.2,pp. 353-363, Feb.2013. ISSN: 10518215, SCI 4.13
32 B.K. Mohanty and P.K.Meher, “A high-performance architecture for FIR adaptive filter based on a new distributed-arithmetic formulation of block least mean square algorithm”, IEEE Transaction on Signal Processing, Vol.61, no.4, pp. 921-932, Feb. 2013. ISSN: 1053587X, SCI 5.028
33 G.S.Maharana, P.K.Meher and B. K. Mohanty, “Efficient systolic architecture for VLSI realization ofHeartly-like transforms”, International Journal of Computers and Application, ISSN: 1206212X, Vol.35, No.1, pp.1-7, Feb.2013, (SCOPUS) 0.13
34 B. K. Mohanty, Anurag Mahajan and P.K.Meher, “Area-power-efficient high-throughput implementation of lifting 2-D DWT”, IEEE Transaction on Circuit and System-II, Express Brief. Vol.59, no.7, pp.434-438,July 2012, ISSN: 15497747, SCI 2.82
35 B.K.MohantyandP.K.Meher, Memory-efficient architecture for 3-D DWT using overlapped grouping of frames, IEEE Transaction on Signal Processing, ISSN:1053587X, Vol.59, No.11, pp. 5605-5616, Nov 2011, SCI 5.028
36 B. K. Mohanty and P.K.Meher, “Memory-efficient modular VLSI architecture for high-throughput and low latency implementation of multilevel lifting 2-D DWT, IEEE Transaction on Signal Processing, Vol.59,No.5, pp.2072-2084, May 2011, SCI 5.028
37 B. K. Mohanty and P.K.Meher, “Parallel and pipeline architecture for high-throughput computation of 3-DDWT, Regular Paper, IEEE Transaction on Circuit and System for Video Technology, ISSN: 10518215, Vol.20, No.9,pp.1200-1209, Sept. 2010. SCI 4.13
38 P.K.Meher, B. K. Mohanty and J.C.Patra, “Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform”, IEEE Transaction on Circuit and System -II, Express Briefs, ISSN: 15497747, Vol.55, No.2, pp.151-154, Feb. 2008, SCI 2.82
39 B. K. Mohanty and P.K.Meher: “High-throughput and low-latency implementation of bit-level systolic architecture for 1-D and 2-D digital filters”, IET Computer and Digital Technique, ISSN: 17518601, Vol. 146, No. 2, pp. 91- 99, March 1999. SCI 0.803
40 B. K. Mohanty and P.K.Meher: “Novel flexible systolic mess architecture for parallel VLSI implementation of finite digital convolution”, IETE Journal of Research, ISSN: 03772063, Vol. 44, No.6, pp.261-266 Nov. 1998. SCI 0.909
41 B. K. Mohanty and P.K.Meher: “Cost-effective novel flexible cell-level systolic architecture for high throughput implementation of 2-D FIR filter”, IET Computer and Digital Technique, ISSN: 17518601, Vol. 143, No.6, pp.436-439, Nov. 1996, SCI 0.803

 

Papers Presented in National/International Conferences

 

 

S.N Paper details Indexed
1 B.K.Mohanty, VivekChaturvedi, VijetaRathore, and T.Srikanthan, “Memory-Access Aware Work-Load Distribution for Peak-Temperature Reduction of 3D Multi-core Embedded Systems”, IEEEInternational Conference on Digital Signal Processing, Singapore, July 2015, pp.1270-1277. DOI: 10.1109/ICDSP.2015.7252085 SCOPUS
2 VivekChaturvedi, B.K.Mohanty, and T.Srikanthan, “Leakage-Aware Intra-Task Dynamic Voltage Scaling Technique for Energy Reduction in Real-Time Embedded Systems”, IEEEInternational Conference on Digital Signal Processing, Singapore, July 2015, pp.1266-1269. DOI: 10.1109/ICDSP.2015.7252084 SCOPUS
3 Carlo Safarian, T.Ogunfunmi, W.J.Kojacky and B.K.Mohanty, “FPGA implementation of LMS-based FIR adaptive filter for real-time digital signal processing applications”, IEEEInternational Conference on Digital Signal Processing, Singapore, July 2015, pp.1251-1254. DOI: 10.1109/ICDSP.2015.7252081 SCOPUS
4 B.K.Mohanty, P.K.Meher, and T. Srikanthan, “Critical-path optimization for efficient hardware realization of lifting and flipping DWTs”, IEEE International Symposium on Circuits and Systems (ISCAS-2015), pp.1186-1189,  May 2015, Portugal, DOI: 10.1109/ISCAS.2015.7168851 SCOPUS
5 P.K.Meher,B.K.Mohanty, and M.N.S.Swamy, “Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT using 9/7 and 5/3 Filters, 28International Conference on VLSI Design, (VLSI-2015), pp.527-533, Bangaluru, India, 3-7 January 2015, DOI: 10.1109/VLSID.2015.61 SCOPUS
6 P.K.Meher, B.K.Mohanty and T. Srikanthan, “Area-Delay Efficient Architecture for MP Algorithm Using Reconfigurable Inner-Product Circuits”, IEEE International Symposium on Circuits and Systems (ISCAS-2014), pp.2628-2631, May 2014, Australia, DOI: 10.1109/ISCAS.2014.6865712 SCOPUS
7 B.K.Mohanty, S.A.Madeed, and A.Amira,  “Systolic architecture for hardware efficient implementation of 2-D non-separable filter bank, In.Proc. International Design and Testing Symposium, Doha, Qatar, Dec.2012, DOI: 10.1109/IDT.2013.6727130 SCOPUS
8 B.K.Mohanty, P.K.Meher and SubodhSinghal, “Efficient architectures for implementation of 2-D discrete Hadamard transform”, In Prco. IEEE International Symposium on Circuits and Systems,ISCAS 2012, pp.1480-1483, Seoul, South Korea, May 2012, DOI: 10.1109/ISCAS.2012.6271527 SCOPUS
9 AnuragMahajan and B.K.Mohanty, Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic, In Proc.  IEEE Asia Pacific Conference on Circuit and Systems, APCCAS-2010, pp. 1195-1198, Malaysia, Dec 5-9, 2010, DOI: 10.1109/APCCAS.2010.5775015 SCOPUS
10 B. K.Mohanty and P.K.Meher,  “Efficient multiplier-less design for 1-D DWT using 9/7 filters based on distributed arithmetic,” IEEE International Symposium on Integrated Circuits (ISIC-2009), pp.364-367, 14-15 Dec, Singapore, 2009, EID: 2-s2.0-77950393791 SCOPUS
11 B. K.Mohanty and P.K.Meher , “DA based bit-serial systolic architecture for 2-D non-separable discrete wavelet transform,”IEEE International Symposium on Integrated Circuits (ISIC-2009), pp.159-162,  14-15 Dec, Singapore, 2009, EID: 2-s2.0-77950446323 SCOPUS
12 B.K.Mohanty and P.K.Meher,  “New scan method and pipeline architecture for VLSI implementation of separable 2-D FIR filters without using transposition,” IEEE Region 10 TENCON2008 Conference, Hyderabad, 2008, DOI: 10.1109/TENCON.2008.4766758 SCOPUS
13 B.K.Mohanty and P.K.Meher, “Delayed block LMS algorithm and concurrent architecture for high-speed implementation of adaptive FIR filters,” IEEE Region 10 TENCON2008 Conference, Hyderabad, Nov. 2008, DOI: 10.1109/TENCON.2008.4766786 SCOPUS
14 B.K.Mohanty and P.K.Meher, “Concurrent systolic architecture for high-throughput implementation of 3-Dimensional discrete wavelet transform”, 19th IEEE International Conference Application-specific Systems, Architectures and Processors, ASAP’08, pp. 168-172, Belgium, 2008, DOI: 10.1109/ASAP.2008.4580172 SCOPUS
15 B.K.Mohanty and P.K.Meher ,  “Throughput-Scalable Hybrid-Pipelined architecture for multilevel lifting 2-D DWT of JPEG 2000 Coder”, 19th IEEE International Conference Application-specific Systems, Architectures and Processors, ASAP’08, pp. 311-315, Belgium, July 2008, DOI: 10.1109/ASAP.2008.4580196 SCOPUS
16 B.K.Mohanty and AnuragMahajan “CSE and CSD based systolic design for low-complexity VLSI implementation of 1-D DWT”, National Conference on Communication System and Networking, CSN-08, JIET, Guna, 2008
17 B. K.Mohanty and P.K.Meher, Bit-serial systolic architecture for 2-D non-separable discrete wavelet transform, IEEE International Conference on Intelligent and Advanced Systems (ICIAS-2007), pp.1355-1358, Malaysia. May 2007, DOI: 10.1109/ICIAS.2007.4658605 SCOPUS
18 B.K.Mohanty and P.K.Meher,  “Pipelined architecture for high-speed implementation of multilevel lifting 2-D DWT using 9/7 filters, IEEE International Symposium on Signal Circuit and Systems, ISSCS2007,pp.137-140, July, Romania, July 2007, DOI: 10.1109/ISSCS.2007.4292670 SCOPUS
19 B.K.Mohanty and P.K.Meher, “Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform” IEEE Asia Pacific Conference on Circuit and Systems, APCCAS-2006, pp.462-465, Singapore, 2006, DOI: 10.1109/APCCAS.2006.342489 SCOPUS
20 B.K.Mohanty and P.K.Meher “VLSI Architecture for High-Speed/Low-Power Implementation of Multilevel Lifting DWT” IEEE Asia Pacific Conference on Circuit and Systems APCCAS-2006, pp. 458-461, Singapore, 2006, DOI: 10.1109/APCCAS.2006.342488 SCOPUS
21 B.K.Mohanty and P.K.Meher  “Bi-layer systolic architecture for bit-serial implementation of Discrete Wavelet Transform”, 10thIEEE International Conference on Communication Systems ICCS 2006,Singapore, 2006, DOI: 10.1109/ICCS.2006.301395 SCOPUS
22 B.K.Mohanty and P.K.Meher, “Systolic architecture for transposition free VLSI implementation of 2-D DWT”, 10thIEEE International Conference on Communication Systems ICCS 2006, Singapore, 2006, DOI: 10.1109/ICCS.2006.301398 SCOPUS
23 B.K.Mohanty: “Recursive Relation and Systolic Architecture for VLSI Implantation of Digit Serial Multiplier”, In Proc. Third National Conference on Applicable Mathematics in Wave Mechanics and Vibrations (WMVC-2006), Oct. 2006, Guna.
24 B.K.Mohanty: “Digit-serial architectures for VLSI implementation of DLMS adaptive FIR filters ”, Accepted at WSEAS 2004 Conferences in Salzburg, AUSTRIA, February 13-15, 2004, (http://www.wseas.us/e-library/conferences/austria2004/papers/482-302.pdf). SCOPUS
25 AnuragMahajanandB.K.Mohanty: “Bit-serial design for VLSI implementation of 1-D discrete wavelet transform using 9/7 filters based on distributed arithmetic”, In Proc. Third CSI National Conference on Education and Research (ConfER 2010), Mar. 6-7, 2010, Guna.

 

Seminars/ Workshops/Conferences Attended:

 

  • IEEE International Design and Testing Symposium, organized by Texas A&M University, Doha, Qatar, Dec. 2012.
  • IEEE Region 10 TENCON 2008 Conference, Organized by University of Hyderabad, Nov.2008.
  • 10th IEEE International Conference on Communication Systems 2006, Organized by Nanayang Technological University in Association with IEEE Singapore Section, Singapore, Oct 2006.
  • IEEE International Conference on Signal Processing and Communication, Jointly organized by JIIT, Noida and IEEE Delhi Section, 2013.
  • International Conference on Signal Processing, (ICSPSATI-2016), Nov.7, 2016, Samrat Ashok Technological Institute (SAATI), Vidisha, Madhya Pradesh.
  • 1-Day workshop on “Project proposal preparation” organized by MPCST, Bhopal, March 7, 2017

 

Professional Activity:

 OTHER ACADEMIC AND CORPORATE ACTIVITIES

Activity Name of the professional body/society/Institution
Associate Editor Circuit, System and Signal Processing, Springer, Impact Factor: 1.93, SCI
Reviewer 1.     IEEE Transaction on Circuit and System-II, Express Brief

2.     IEEE Transaction on Circuit and System-I, Regular Papers

3.     IEEE Transaction on Very Large Scale Integration (VLSI) Systems

4.     IEEE Transaction on Circuit and System for Video Technology

5.     IEEE Transaction on Signal Processing

6.     IEEE Transaction on Computers

7.     IET Circuit Device and Technology/Signal Processing/Image Processing.

8.     Journal of Circuit, System and Signal Processing, Springer

9.     Integration, the VLSI Journal, Elsevier

10.  Journal of Real-Time Image Processing, Elsevier

11.  Engineering Sciences Technology, an International Journal, Elsevier

12.  Microprocessor and Microsystems, Elsevier

13.  ISCAS: International Symposium on Circuits and Systems (the annual flagship event of Circuit and System Society, IEEE)

Categories: Faculty
Updated 3 months ago.